华中科技大学学报（自然科学版）2024，Vol.52Issue(3)：7-13,7.DOI:10.13245/j.hust.240079
RISC-VAES扩展指令的硅前评估与安全增强
Pre-silicon evaluation and security enhancement for RISC-V AES extensions
摘要
Abstract
The instruction set architecture(ISA)extension for cryptographic algorithm acceleration may introduce the risk of side channel leakage.A side channel security evaluation process in the pre-silicon stage was proposed,which could accurately locate the time and microarchitecture components with side channel leakage risk during the processor operation.Based on a 32 bit in-order reduced instruction set compute(RISC-V)processor architecture,two representative advanced encryption standard(AES)extension instructions and extended hardware circuits were implemented,and then the proposed evaluation method was applied to evaluate the side channel security.Based on the evaluation results,a hybrid protection strategy of extension port dynamic mask and power randomization of the operation unit was proposed,and the pre-silicon security verification was carried out.Finally the AES ISA extension with high side channel security was realized.The experimental results show that the proposed hybrid protection strategy can improve the side channel security of the AES extension by 1 886 times and more under the 4.9％area overhead.关键词
硅前侧信道/高级加密标准(AES)/扩展指令/精简指令集计算机(RISC-V)/相关性功耗分析Key words
pre-silicon side channel/advanced encryption standard(AES)/extension instructions/reduced instruction set compute(RISC-V)/correlation power analysis分类
信息技术与安全科学引用本文复制引用
赵毅强,魏鑫,李尧,何家骥..RISC-VAES扩展指令的硅前评估与安全增强[J].华中科技大学学报（自然科学版）,2024,52(3):7-13,7.基金项目
国家重点研发计划资助项目(2021YFB3100903). （2021YFB3100903）
