华中科技大学学报（自然科学版）2024，Vol.52Issue(3)：14-19,27,7.DOI:10.13245/j.hust.240301
基于二值忆阻器的三值逻辑门和乘法器设计
Ternary logic gate and multiplier design based on binary memristor
摘要
Abstract
In order to reduce the power consumption of logic circuits and increase the information density of digital logic circuits,the SPICE circuit model of Knowm's memristor was established which was based on the electrical characteristics of the binary-type memristor.LTspice simulation software was used to verify the validity of the circuit model.After that,the model was used to establish three-valued basic logic gate,and the validity of the basic logic gate was verified.Finally,the three-valued multiplier circuit based on the memristor was constructed on this basis,and the simulation and power analysis were performed in LTspice simulation software.In this paper,the three-valued basic logic gate and three-valued multiplier are designed by using binary memristors.Compared with the N-well three-valued complementary metal oxide semiconductor(CMOS)logic gate circuit,this scheme has the advantages of high performance and lower delay,high integration and low power consumption,and can be used to replace the logic circuit composed of traditional CMOS tubes.关键词
忆阻器/三值逻辑门/乘法器/基本逻辑门/仿真Key words
memristor/ternary logic gate/multiplier/basic logic gate/simulation分类
信息技术与安全科学引用本文复制引用
吴建新,朱逸琨,钟祎..基于二值忆阻器的三值逻辑门和乘法器设计[J].华中科技大学学报（自然科学版）,2024,52(3):14-19,27,7.基金项目
国家自然科学基金资助项目(62071190) （62071190）
华中科技大学实验技术研究项目(202435). （202435）
