一款400 μm2用于极短距离接收机具有中频补偿的56 Gb/s PAM4反相器型连续时间线性均衡器OACSTPCD

High-speed extra short reach(XSR)wireline interfaces are an important technical solution for chiplets interconnection.The traditional continuous time linear equalizer(CTLE)based on current mode logic(CML)has gradually failed to meet the demand for high-density,miniaturization,and low-power consumption of chiplet data interfaces due to the use of high supply voltage and passive com-ponents.To address this problem,this paper proposes an inverter-based CTLE with mid-frequency compensation(MFC)to transmit 28 Gb/s non-return to zero(NRZ)signals as well as 56 Gb/s 4-level pulse amplitude modulation(PAM4)signals in XSR applications.The design is implemented in a 28 nm CMOS process with a core area of only 400 μm2.After an XSR channel at-9.4 dB@14 GHz,the post-layout simulation results show that the proposed CTLE improves the eye width of the 28 Gbaud NRZ and PAM4 signals by 0.14 UI and 0.41 UI,and the eye heights by 328 mV and 119 mV,respectively.The power consumption is 6.12 mW at 56 Gb/s PAM4 signaling.