ESD保护电路在HDMI板级信号完整性中的影响分析及其布局优化研究OACSTPCD
Research on influence analysis and layout optimization of ESD protection circuits on signal integrity at HDMI board level
为了解决HDMI接入ESD保护电路后信号完整性受破坏等问题,从器件的空间布局对HDMI信号完整性影响进行研究分析,同时考虑了瞬态电压抑制(TVS)高频寄生参数的影响,搭建了ESD放电模型和TVS高频等效电路模型,并对其可靠性进行了验证.从差分器件接入信号线旋转角度和彼此间错开距离研究其对信号完整性的影响,设计了25套不同夹角和4套不同错开距离的板级模型,在不同特性的传输频率下进行S参数仿真,并从中选取出垂直型、水平型、错开型三种具有代表性的空间布局模型,利用有限元仿真得到差分信号线的S参数和眼图.仿真结果表明,垂直型排布相比于其他两种典型空间布局,回波损耗平均降低了248.1%,插入损耗平均降低了20.6%,眼图的眼宽和眼高在三种空间布局中最大.研究成果为PCB静电放电保护电路分析与设计提供了布局优化指导.
In order to solve the problem of signal integrity damage after HDMI is connected to ESD(electrostatic discharge)protection circuits,the effectegrity of HDMI signal is analyzed.Considering the influence of high-frequency parasitic parameters in transient voltage suppression(TVS),the ESD discharge model and TVS high frequency equivalent circuit model are established and their reliability is verified.The influence on signal integrity was studied from rotation angle and staggered distance of differential device access signal lines.Twenty-five sets of plate-level models with different angles and four sets of different staggered distances are designed,and S-parameter simulation is carried out under different transmission frequencies with different characteristics.Three representative spatial layout models,vertical,horizontal,and staggered,are selected.The S-parameter and the eye chart of the difference signal line were obtained by means of the finite element simulation.The simulation results show that,compared with the other two typical spatial layouts,the return loss and insertion loss of the vertical layout are reduced by 248.1%and 20.6%on average.The eye width and eye height of the eye chart are the largest among the three spatial layouts.The results provide layout optimization guidance for the analysis and design of PCB electrostatic discharge protection circuits.
王淼;李嘉豪;汤浩;郭亚
江南大学 物联网工程学院 “轻工过程先进控制”教育部重点实验室,江苏 无锡 214122
电子信息工程
静电放电(ESD)HDMI信号完整性空间布局优化瞬态电压抑制(TVS)S参数有限元仿真
ESDHDMIsignal integrityspatial layout optimizationTVSS parameterfinite element simulation
《现代电子技术》 2024 (008)
68-74 / 7
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