雷达科学与技术2024，Vol.22Issue(2)：231-236,6.DOI:10.3969/j.issn.1672-2337.2024.02.014
基于16相快速滤波实现采样率4～8GS/s中频信号预处理
Implementation of 4～8 GS/s Intermediate Frequency Sampling Signal Preprocessing with 16-Phase Fast Filter
王利华 1赵微微1
作者信息
- 1. 中国航空工业集团公司雷华电子技术研究所,江苏无锡 214063
- 折叠
摘要
Abstract
In the preprocessing of large bandwidth digital intermediate frequency(IF)signals in the airborne radar or electronic warfare receiving system,the traditional parallel polyphase filtering has the drawback of consuming exces-sive FPGA's multiplier resource.A method with construction of fast filtering algorithm by parallel polyphase decomposi-tion coefficients is proposed to realize digital down conversion(DDC)processing of high-speed ADC sampling rate between 4 GS/s and 8 GS/s.First,the IF sampling signal is decomposed into 32 parallel branches.Then,the parallelism of the baseband complex signal is reduced to 16 through digital mixing and double decimation.Finally,to realize DDC processing of high sampling rate and large bandwidth signal,the 16-phase fast filtering architecture based on the short convolution algorithm is constructed.Through the design and application of wideband DDC based on 16-phase fast filtering,the FPGA multiplier resource is reduced to about 32%of the traditional parallel polyphase filtering,which greatly saves FPGA's resource and improves the preprocessing ability of single FPGA for multi-channel and large bandwidth signals.关键词
采样率/16相快速滤波/数字下变频/FPGAKey words
sampling rate/16-phase fast filter/digital down conversion/FPGA分类
电子信息工程引用本文复制引用
王利华,赵微微..基于16相快速滤波实现采样率4～8GS/s中频信号预处理[J].雷达科学与技术,2024,22(2):231-236,6.
