现代信息科技2024，Vol.8Issue(7)：11-14,18,5.DOI:10.19850/j.cnki.2096-4706.2024.07.003
DVB-T中伪随机序列扰码器的FPGA实现
FPGA Implementation of Pseudo-random Sequence Scrambler in DVB-T
陈振林1
作者信息
- 1. 佛山职业技术学院 电子信息学院,广东 佛山 528137
- 折叠
摘要
Abstract
Pseudo-random sequence is widely used in pseudo-code ranging,navigation,digital data scramblers,noise generators and communication encryption.In the practical application,the FPGA is usually used to generate pseudo-random sequences,which can bring great convenience to system design or testing.Aiming at the DVB-T standard,based on the linear feedback shift register circuit,a simple and efficient parallel pseudo-random sequence generation method is designed to realize the scrambling of DVB-T system code flow data.The experimental results show that the MATLAB scrambling algorithm results are consistent with the FPGA scrambling module simulation results and hardware implementation results,so the design method is feasible.关键词
伪随机序列/DVB-T/MATLAB/FPGA/VerilogKey words
pseudo-random sequence/DVB-T/MATLAB/FPGA/Verilog分类
信息技术与安全科学引用本文复制引用
陈振林..DVB-T中伪随机序列扰码器的FPGA实现[J].现代信息科技,2024,8(7):11-14,18,5.
