郑州大学学报（工学版）2024，Vol.45Issue(3)：96-102,7.DOI:10.13705/j.issn.1671-6833.2023.06.001
一种基于FPGA的SVPWM硬件架构及其计算速度优化
A SVPWM Hardware Architecture Based on FPGA and Its Computational Speed Optimization
摘要
Abstract
In order to improve the modulation speed of seven segment two-level SVPWM algorithm and reduce the use of logic resources,a hardware architecture of SVPWM based on FPGA was proposed.After inputting the refer-ence voltage,the hardware architecture first carried out the coordinate transformation based on the inverse Clarke transform,constructed three groups of intermediate variables containing three-phase duty cycle through a series of addition operations,and obtained the simplified 2 bit sector judgment conditions from the above hardware wiring through two XOR operations.Then,according to the simplified 2 bit sector judgment conditions,the three-phase duty cycle was selected from the above three groups of intermediate variables,and clamp protection was carried out,and PWM was output according to the natural sampling method.The above process formed a whole.The whole process from reference voltage input to three-phase PWM output had been completed in two clock cycles with only three triggers in FPGA,which effectively improved the calculation speed.In addition,the resource usage of the hardware architecture with different FPGA platforms was also given.Compared with other methods,the LUT usage was reduced from at least 500 to about 300,and the logical resource usage was reduced.The effectiveness of the proposed hardware architecture was verified by simulation and physical test.关键词
SVPWM/硬件架构/Clarke逆变换/FPGA/计算速度优化Key words
SVPWM/hardware architecture/inverse Clarke transform/FPGA/optimization of computing speed分类
信息技术与安全科学引用本文复制引用
刘德平,辛云川,刘子旭..一种基于FPGA的SVPWM硬件架构及其计算速度优化[J].郑州大学学报（工学版）,2024,45(3):96-102,7.基金项目
河南省重大科技专项资助项目(171100210300-01) （171100210300-01）
