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面向国产处理器的FPGA原型验证系统优化方法

褚捃博

信息工程大学学报2024,Vol.25Issue(2):155-161,7.
信息工程大学学报2024,Vol.25Issue(2):155-161,7.DOI:10.3969/j.issn.1671-0673.2024.02.005

面向国产处理器的FPGA原型验证系统优化方法

Optimization Method of FPGA Prototype Verification System for Domestic Processor

褚捃博1

作者信息

  • 1. 信息工程大学,河南郑州 450001
  • 折叠

摘要

Abstract

Field programmable gate array(FP GA)verification is a necessary step in the design of in-tegrated circuits.In the FPGA verification of a home-made processor chip,the test results of some performance test subjects are unstable,and the results differ greatly from those of other verification platforms.To solve this problem,a new debugging system based on transaction processing module is developed,which can easily and accurately observe the dynamic changes of key transactions in FP-GA testing process and real-time transmission.Using transaction-level error checking method instead of common signal-level error checking method,the observability of FPGA prototype verification process is effectively improved,the speed of problem location is accelerated,and the efficiency of error checking and verification is improved.In the verification process of the target processor chip,the problem of unstable testing of the second-level cache memory access delay has been successfully solved,and some achievements have been made.

关键词

FPGA原型验证/FPGA调试方法/事务处理模块

Key words

FPGA prototype verification/FPGA debugging method/transaction

分类

信息技术与安全科学

引用本文复制引用

褚捃博..面向国产处理器的FPGA原型验证系统优化方法[J].信息工程大学学报,2024,25(2):155-161,7.

信息工程大学学报

1671-0673

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