集成电路与嵌入式系统2024，Vol.24Issue(5)：42-47,6.
应用于高速图像传感器的高线性度Latch-ADC
High linearity Latch-ADC for high-speed image sensors
摘要
Abstract
Aiming at the requirement of high-speed and high linearity of CMOS image sensor for high-speed application devices,this paper realizes a Latch-ADC applied to image sensor on the basis of traditional SS ADC(Single-Slope ADC,Single-Slope analog-to-digital con-verter),with an operating frequency of 600 MHz.Latch-ADC can use multi-column pixels to share a Gray Code Counter,and quickly lock and store data through Latch structure,which realizes the functions of counter and SRAM in SS ADC.In this paper,a high-speed 12bit Latch-ADC is implemented by using 110 nm technology.Through simulation verification,the Latch-ADC in this paper has high linearity,with each conversion period of 7.094 μs,average power of 180.3 μW,and conversion power consumption of 1.279 nJ.关键词
高速应用设备/CMOS图像传感器/SS ADC/高线性度/Latch-ADCKey words
high speed application devices/CMOS image sensor/SS ADC/high linearity/Latch-ADC分类
信息技术与安全科学引用本文复制引用
潘佳明,熊波涛,李兆涵,常玉春..应用于高速图像传感器的高线性度Latch-ADC[J].集成电路与嵌入式系统,2024,24(5):42-47,6.基金项目
国家自然科学基金(62027826). （62027826）
