面向高帧率CMOS图像传感器的12位列级全差分SAR/SS ADC设计OACSTPCD

Aiming at the application requirements of high frame rate CMOS image sensors,a hybrid analog-to-digital converter(ADC)combining successive approximation register(SAR)and single slope(SS)structures is proposed.The resolution of this ADC is 12-bit,with SAR ADC achieving high 6-bit quantization and SS ADC achieving low 6-bit quantization.The ADC adopts a fully differential struc-ture to eliminate fixed misalignment of the sampling switch and reduce nonlinear errors.At the same time,asynchronous logic circuits are used in SAR ADC to further shorten the conversion cycle.The circuit is designed and implemented using 110 nm 1P4M CMOS technolo-gy.The post-layout simulation results show that at clock frequency of 20 MHz,the conversion period is only 3.3 μs,the spurious free dy-namic range is 77.12 dB,the signal-to-noise distortion ratio is 67.38 dB,and the effective bit is 10.90 bits.