集成电路与嵌入式系统2024，Vol.24Issue(5)：48-54,7.
面向高帧率CMOS图像传感器的12位列级全差分SAR/SS ADC设计
Design of a 12-bit column level fully differential SAR/SS ADC for high-frame rate CMOS image sensors
摘要
Abstract
Aiming at the application requirements of high frame rate CMOS image sensors,a hybrid analog-to-digital converter(ADC)combining successive approximation register(SAR)and single slope(SS)structures is proposed.The resolution of this ADC is 12-bit,with SAR ADC achieving high 6-bit quantization and SS ADC achieving low 6-bit quantization.The ADC adopts a fully differential struc-ture to eliminate fixed misalignment of the sampling switch and reduce nonlinear errors.At the same time,asynchronous logic circuits are used in SAR ADC to further shorten the conversion cycle.The circuit is designed and implemented using 110 nm 1P4M CMOS technolo-gy.The post-layout simulation results show that at clock frequency of 20 MHz,the conversion period is only 3.3 μs,the spurious free dy-namic range is 77.12 dB,the signal-to-noise distortion ratio is 67.38 dB,and the effective bit is 10.90 bits.关键词
高帧率CMOS图像传感器/混合型列ADC/单斜ADC/逐次逼近型ADC/电流舵DACKey words
high-frame rate CMOS image sensor/hybrid column level ADC/single slope ADC/sequential approximation register ADC/current steering DAC分类
信息技术与安全科学引用本文复制引用
牛志强,陈志坤,胡子阳,王刚,刘剑,吴南健,冯鹏..面向高帧率CMOS图像传感器的12位列级全差分SAR/SS ADC设计[J].集成电路与嵌入式系统,2024,24(5):48-54,7.基金项目
国家自然科学基金重点项目(62134004). （62134004）
