宇航用总线型上注刷新ASIC的设计OACSTPCD

In current aerospace missions,the SRAM-based FPGA is susceptible to single-event effects,resulting in unexpected functional failures.In order to mitigate the impact of single-event effects and reduce the workload of repetitive design and testing,a bus-based FPGA program upload-scrubbing ASIC is designed.The ASIC supports multiple buses,adapts to various FPGAs,and is compatible with different memory types.It is utilized for tasks such as FPGA program loading,scrubbing,program upload,and other on-orbit mainte-nance operations.Firstly,the ASIC's system-level design,module-level design,and workflow planning are presented.The principle of ASIC resistance to single-event effects is briefly described.By designing compatible communication protocols,the ASIC simultaneously supports CAN bus and RS485 bus.By analyzing the FPGA configuration bitstream structure,the ASIC supports loading and scrubbing 9 types of FPGAs and achieves domestic compatibility.By converting the data format of memory,the ASIC can store the configuration bits-tream in various memories,including BPI Flash,SPI Flash,PROM,and others.The triggering of scrubbing,SEFI detection,and execu-tion of scrubbing are discussed.Analyzing and simulating the factors affecting the upload speed of the ASIC.Utilize prototype verification board,ASIC verification board,and pluggable FPGAs and memory floating small boards to complete various functional verifications be-fore and after tape-out.The verification results are as expected.The effectiveness of the scrubbing is evaluated and compared with other on-orbit maintenance schemes.The bus-based program upload-scrubbing ASIC has certain advantages and can efficiently and reliably meet the various on-orbit maintenance requirements of aerospace FPGA.