A frequency servo SoC with output power stabilization loop technology for miniaturized atomic clocksOACSTPCDEI
A frequency servo system-on-chip(FS-SoC)featuring output power stabilization technology is introduced in this study for high-precision and miniaturized cesium(Cs)atomic clocks.The proposed power stabilization loop(PSL)technique,incorporating an off-chip power detector(PD),ensures that the output power of the FS-SoC remains stable,mitigating the impact of power fluctuations on the atomic clock''s stability.Additionally,a one-pulse-per-second(1PPS)is employed to syn-chronize the clock with GPS.Fabricated using 65 nm CMOS technology,the measured phase noise of the FS-SoC stands at-69.5 dBc/Hz@100 Hz offset and-83.9 dBc/Hz@1 kHz offset,accompanied by a power dissipation of 19.7 mW.The Cs atomic clock employing the proposed FS-SoC and PSL obtains an Allan deviation of 1.7×10^(-11) with 1-s averaging time.
Hongyang Zhang;Xinlin Geng;Zonglin Ye;Kailei Wang;Qian Xie;Zheng Wang
School of Integrated Circuit Science and Engineering,University of Electronic Science and Technology of China,Chengdu 611731,ChinaSchool of Integrated Circuit Science and Engineering,University of Electronic Science and Technology of China,Chengdu 611731,ChinaSchool of Integrated Circuit Science and Engineering,University of Electronic Science and Technology of China,Chengdu 611731,ChinaSchool of Integrated Circuit Science and Engineering,University of Electronic Science and Technology of China,Chengdu 611731,ChinaSchool of Integrated Circuit Science and Engineering,University of Electronic Science and Technology of China,Chengdu 611731,ChinaSchool of Integrated Circuit Science and Engineering,University of Electronic Science and Technology of China,Chengdu 611731,China
电子信息工程
CMOS technologyatomic clockphase-locked loopoutput power stabilization1PPS
《Journal of Semiconductors》 2024 (6)
P.13-22,10
supported by the National Natural Science Foundation of China under Grant 62034002 and 62374026.
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