A 16-bit 18-MSPS flash-assisted SAR ADC with hybrid synchronous and asynchronous control logicOACSTPCDEI
This paper presents a 16-bit,18-MSPS(million samples per second)flash-assisted successive-approximation-register(SAR)analog-to-digital converter(ADC)utilizing hybrid synchronous and asynchronous(HYSAS)timing control logic bas…查看全部>>
Junyao Ji;Xinao Ji;Ziyu Zhou;Zhichao Dai;Xuhui Chen;Jie Zhang;Zheng Jiang;Hong Zhang
School of Microelectronics,Xi''an Jiaotong University,Xi''an 710049,ChinaSchool of Microelectronics,Xi''an Jiaotong University,Xi''an 710049,ChinaSchool of Microelectronics,Xi''an Jiaotong University,Xi''an 710049,ChinaQingdao Hi-image Tech.Co.Ltd.,Qingdao 266100,ChinaQingdao Hi-image Tech.Co.Ltd.,Qingdao 266100,ChinaSchool of Microelectronics,Xi''an Jiaotong University,Xi''an 710049,ChinaQingdao Hi-image Tech.Co.Ltd.,Qingdao 266100,ChinaSchool of Microelectronics,Xi''an Jiaotong University,Xi''an 710049,China
电子信息工程
SAR ADCcontrol logicreference ringingDAC incomplete settling
《Journal of Semiconductors》 2024 (6)
P.3-12,10
supported by Qingdao Hi-image Technologies Co.,Ltd,and in part by the NSFC of China under Grant 62174149,61974118,62004156the National Key R&D Program of China under Grant 2022YFC2404902.
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