集成电路与嵌入式系统2024，Vol.24Issue(6)：41-45,5.
一种高效16位有符号数乘法器设计
Design and implementation of an efficient 16-bit signed number multiplier
摘要
Abstract
To further optimize the performance of the multiplier and improve the operation speed of the multiplication unit,an improved 16-bit signed number multiplier is designed based on the Radix-4 Booth algorithm and Wallace tree compression structure.Its charac-teristics are:optimize the Radix-4 Booth encoding method to effectively reduce the area of partial product selection circuits.Improve the partial product calculation process by optimizing the inverse plus one method to directly generate the opposite of the multiplicand,at the same time,use the classic sign bit compensation algorithm to make the partial product array regular and easy to compress.A new type of 4-2 compressor is proposed,which uses a single full adder to process the middle carry of the compressor.The Wallace tree compression structure is refined to improve the compression efficiency of partial products for different data features in each row.Synthesis and verified based on SMIC 180 nm standard cell library,the results show that the critical path delay of the multiplier designed in this paper is 3.94 ns,with an area of 16 246 pm2.Compared to existing multipliers,the computational speed and overall performance of the multiplier in this paper have been significantly improved.关键词
乘法器/Booth算法/部分积/Wallace树/压缩器Key words
multiplier/Booth algorithm/partial product/Wallace tree/compressor分类
信息技术与安全科学引用本文复制引用
李娅妮,郎世坤,王雅,师瑞之..一种高效16位有符号数乘法器设计[J].集成电路与嵌入式系统,2024,24(6):41-45,5.
