舰船电子工程2024，Vol.44Issue(3)：160-164,186,6.DOI:10.3969/j.issn.1672-9730.2024.03.035
基于UVM的总线桥接模块验证
Bus Bridge Module Verification Based on UVM
摘要
Abstract
With the progress of integrated circuit technology and design level,the scale and complexity of integrated circuit have been greatly increased,so it is difficult to meet the requirements of functional verification in chip development by using tradi-tional verification methods.Based on the UVM verification methodology,this paper studies the verification of bus bridge module in system-level chip.Firstly,the functional features and interface signals of the module are analyzed,and the UVM verification plat-form is built.Then,test-cases are written to test all functional points of the module,and the design is modified according to the test results.The regression test is carried out after all test cases passed.The regression test results showes that code coverage reached 98%and function coverage reached 100%,meeting the verification requirements.After this verification,the function of the module has been fully verified,and can be successfully applied to the on-chip interconnection of system-level chips.Meanwhile,the verifi-cation platform built in this time has certain universality and re-usability.关键词
集成电路/功能验证/UVM/AMBA/可重用性Key words
integrated circuit/functional verification/UVM/AMBA/re-usability分类
信息技术与安全科学引用本文复制引用
毛国栋,郭涛,梁颖,陈梦凡,石帅..基于UVM的总线桥接模块验证[J].舰船电子工程,2024,44(3):160-164,186,6.基金项目
国家自然科学基金项目(编号:51975541)资助. （编号:51975541）
