哈尔滨工业大学学报（英文版）2024，Vol.31Issue(3)：31-38,8.DOI:10.11916/j.issn.1005-9113.2023071
Area-Optimized BCD-4221 VSLI Adder Architecture for High-Performance Computing
Area-Optimized BCD-4221 VSLI Adder Architecture for High-Performance Computing
Dharamvir Kumar 1Manoranjan Pradhan1
作者信息
- 1. Department of Electronics&Telecommunication Engineering,Veer Surendra Sai University of Technology,Burla 768018,India
- 折叠
摘要
关键词
VLSI design/unconventional BCD representation/BCD adder circuit/computer arithmetic/digital circuitKey words
VLSI design/unconventional BCD representation/BCD adder circuit/computer arithmetic/digital circuit分类
信息技术与安全科学引用本文复制引用
Dharamvir Kumar,Manoranjan Pradhan..Area-Optimized BCD-4221 VSLI Adder Architecture for High-Performance Computing[J].哈尔滨工业大学学报（英文版）,2024,31(3):31-38,8.
