湖南大学学报（自然科学版）2024，Vol.51Issue(6)：187-194,8.DOI:10.16339/j.cnki.hdxbzkb.2024238
基于RISC-V的IOMMU设计
Design of IOMMU Based on RISC-V
摘要
Abstract
In the realm of semiconductor technology control,achieving complete autonomous chip control has emerged as a focal point in today's semiconductor technology advancement.Given its features of open source and widespread adoption,the study of RISC-V architecture holds significant importance for enabling microprocessor autonomous controllability.Within microprocessor systems,limitations on physical resources and potential risks associated with direct storage access necessitate restrictions on DMA access to I/O devices,thereby impacting access performance.The prevailing approach involves virtualizing I/O transactions to effectively address this issue.This article firstly proposes a I/O virtualization architecture based on RISC-V,which greatly accelerates the I/O access process,this architectrue consums a few clock period to complete DMA requests from I/O devices to memory.This design will be integrated into RISC-V architecture CPU as an IP,accelerating the access of I/O devices to memory.关键词
虚拟化/缓存/RISC-VKey words
virtualization/cache memory/RISC-V分类
计算机与自动化引用本文复制引用
王镇道,班贵龙,胡锦,焦旭峰..基于RISC-V的IOMMU设计[J].湖南大学学报（自然科学版）,2024,51(6):187-194,8.基金项目
国家自然科学基金资助项目(Z202301432394),National Natural Science Foundation of China(Z202301432394) （Z202301432394）
