集成电路与嵌入式系统2024，Vol.24Issue(7)：43-47,5.
扇出型晶圆级封装重布线层互联结构失效分析
Failure analysis of interconnect structure in redistribution layer of fan-out wafer level packaging
范懿锋 1明雪飞 2曹瑞 1王智彬 1孟猛1
作者信息
- 1. 中国航天宇航元器件工程中心,北京 100098
- 2. 中国电子科技集团第58研究所,无锡 214035
- 折叠
摘要
Abstract
In this study,a series of fan-out wafer-level packaging daisy chain test chips with various dimensions and specifications were fabricated.Temperature cycling tests were conducted on samples under different geometric parameters.Failure analysis of the failed samples was performed using techniques such as metallographic microscopy,scanning electron microscopy(SEM),and energy-disper-sive X-ray spectroscopy(EDS).The failure modes of the redistribution layer interconnect structures in fan-out WLP were systematically investigated and summarized.This research provides guidance for reliability evaluation and high-reliability applications of fan-out WLP products.关键词
扇出型晶圆级封装/可靠性/失效分析/重布线层Key words
fan-out packaging/reliability/failure analysis/redistribution layer分类
信息技术与安全科学引用本文复制引用
范懿锋,明雪飞,曹瑞,王智彬,孟猛..扇出型晶圆级封装重布线层互联结构失效分析[J].集成电路与嵌入式系统,2024,24(7):43-47,5.
