集成电路与嵌入式系统2024，Vol.24Issue(7)：80-84,5.
敏捷开发的SM4算法FPGA实现与优化
SM4 algorithm FPGA implementation and optimization with agile development
聂怀昊 1韩跃平 1李可欣1
作者信息
- 1. 中北大学信息与通信工程学院,太原 030051
- 折叠
摘要
Abstract
This article uses agile development technology to design and improve the SM4 algorithm,and completes the implementation and verification on the Xilinx FPGA platform.In view of the shortcomings of the SM4 algorithm featuring long critical path and low throughput,a register group consisting of 32 registers is inserted into the round function calculation process as a cache area,and the pipe-line method is used to shorten the critical path and optimize the S-box module structure,thus greatly improving the work efficiency.Fre-quency and throughput reach 340 MHz and 1.2 Gbit/s,respectively.At the same time,the new high-level hardware description language BSV is used for development,which greatly reduces the design complexity.Compared with the design using Verilog,the performance is 40％higher and the complexity is 60％lower without notable difference in hardware overhead.Compared with the earlier solution,the resource overhead is reduced by 70％,the performance is doubled,and it has higher application value.关键词
敏捷开发/BSV/SM4/关键路径/FPGAKey words
agile development/BSV/SM4/critical path/FPGA分类
信息技术与安全科学引用本文复制引用
聂怀昊,韩跃平,李可欣..敏捷开发的SM4算法FPGA实现与优化[J].集成电路与嵌入式系统,2024,24(7):80-84,5.
