基于ZYNQ-7000的飞控计算机PC/104总线数传链路设计OA北大核心CSTPCD

In allusion to the problem of insufficient inherent performance and poor scalability of the original flight control computer caused by the development of multi-module and multi-type interface resources,a flight control computer framework based on ARM+FPGA hardware and software cooperation and taking PC/104 as a multi-module communication bus is proposed.In this framework,a dual-channel data buffer path is designed to improve the bandwidth mismatch between PC/104 bus and system main memory transmission.The PC/104 bus control is realized by IP designed in FPGA,and the high-speed data cache between bus and main memory is realized by means of DMA.The experimental results show that the designed flight control computer data link can realize 40 Mb/s data transmission speed between PC/104 buse between modules,and realize high-speed data exchange with microsecond delay between peripherals and system main memory by the bus,which ensures the data transmission efficiency of multi-module operation.