无线电通信技术2024，Vol.50Issue(4)：647-654,8.DOI:10.3969/j.issn.1003-3114.2024.04.005
物联网场景下基于半并行结构的极化码译码器设计
Design of Polar Decoder on Semi-parallel Architecture in IoT Scenario
摘要
Abstract
Polar codes have attracted widespread attention due to their capacity-achieving property and low encoding and decoding complexity.An improved semi-parallel polar code decoder is proposed for resource-constrained Internet of Things(IoT)communication scenarios,employing a 4 bit decoding algorithm and pre-computation techniques to reduce latency associated with traditional semi-paral-lel architectures,resulting in low decoding latency and high hardware resource utilization efficiency.Experimental results show that for(1024,512)polar codes,compared to traditional semi-parallel decoders and tree-structured 2 bit decoders,the latency of this decoder is re-duced by 48.64％and 75.19％respectively.The hardware resource utilization rate of processing element is increased by 68.42％and 119.35％.The hardware resources are utilized more efficiently,suitable for hardware-constrained IoT scenarios.关键词
极化码译码/无线通信/物联网应用/硬件结构Key words
polar decoding/wireless communication/applications of IoT/hardware architecture分类
信息技术与安全科学引用本文复制引用
郭晶,李聪端..物联网场景下基于半并行结构的极化码译码器设计[J].无线电通信技术,2024,50(4):647-654,8.基金项目
国家自然科学基金(62271514)National Natural Science Foundation of China(62271514) （62271514）
