集成电路与嵌入式系统2024，Vol.24Issue(8)：7-13,7.DOI:10.20193/j.ices2097-4191.2023.0007
应用于低功耗模/数转换器的低电源电压时间域比较器
Low supply voltage time-domain comparators for low power analog-to-digital converters
摘要
Abstract
To address issues of large delay and high power consumption in the Successive Approximation Analog-to-Digital Converter(SAR ADC)voltage-domain comparator,a-low-power-time-domain-comparator is designed in this paper.By introducing a high-gain Time Amplifier(TA),the comparator achieved an exponential increase in phase accumulation speed.This effectively reducing the number of oscillation cycles required for the input signal phase to exit the"dead zone"of the phase discriminator,thereby shortening the comparison delay and optimizing the speed and power consumption.The comparator is designed based on a 65 nm CMOS process and consumes only 5.24 nW at 0.4 V supply voltage and 5.99 mV offset voltage.关键词
SAR ADC/时间域比较器/时间放大器/SR锁存器/鉴相器Key words
SAR ADC/time-domain comparator/time amplifier/set-reset-latch/phase detector分类
信息技术与安全科学引用本文复制引用
蓝宏健,杨建行,王霖伟,李振,周荣,刘术彬..应用于低功耗模/数转换器的低电源电压时间域比较器[J].集成电路与嵌入式系统,2024,24(8):7-13,7.基金项目
中央高校基本科研业务费专项基金资助(XJSJ230460). （XJSJ230460）
