应用于低功耗模/数转换器的低电源电压时间域比较器OACSTPCD

To address issues of large delay and high power consumption in the Successive Approximation Analog-to-Digital Converter(SAR ADC)voltage-domain comparator,a-low-power-time-domain-comparator is designed in this paper.By introducing a high-gain Time Amplifier(TA),the comparator achieved an exponential increase in phase accumulation speed.This effectively reducing the number of oscillation cycles required for the input signal phase to exit the"dead zone"of the phase discriminator,thereby shortening the comparison delay and optimizing the speed and power consumption.The comparator is designed based on a 65 nm CMOS process and consumes only 5.24 nW at 0.4 V supply voltage and 5.99 mV offset voltage.