高技术通讯2024，Vol.34Issue(7)：744-754,11.DOI:10.3772/j.issn.1002-0470.2024.07.008
基于片上系统的可配置卷积神经网络加速器的设计与实现
Design and implementation of configurable CNN accelerator based on SoC
摘要
Abstract
A configurable convolutional neural network(CNN)accelerator based on system of chip(SoC)is designed to address the issue that the current design of CNN accelerators can only be deployed within a single field programma-ble gate array(FPGA)and cannot be used across platforms.The accelerator has two characteristics.First,in the circuit design,data bit width,intermediate buffer space size,and multiply accumulate(MAC)array parallelism are optional configuration parameters.By adjusting the resource utilization,the accelerator can adapt to different FPGA hardware.Second,a dynamic data reuse strategy is proposed to reduce the waiting time for data transmission and improve the utilization of the MAC array by dynamically selecting the reuse method based on the difference in total parameter amounts between different reuse methods during data transmission.The scheme is tested on the ZCU104 board,and the experimental results show that when the data bit width is 8,the multiplier array parallelism is 1 024,and the core operation module works at 180 MHz,the peak throughput of the convolution operation array is 180 GOPs,with a power consumption of 3.75 W,and an energy efficiency ratio of 47.97 GOPs·W-1.For the VGG16 network,the average MAC utilization rate of its convolutional layers reaches 84.37％.关键词
卷积神经网络(CNN)/现场可编程门阵列(FPGA)/CNN加速器/可配置/异构加速Key words
convolutional neural network(CNN)/field programmable gate array(FPGA)/CNN accelerator/configurable/isomerization acceleration引用本文复制引用
张立国,杨红光,金梅,申前..基于片上系统的可配置卷积神经网络加速器的设计与实现[J].高技术通讯,2024,34(7):744-754,11.基金项目
国家重点研发计划(2020YFB1711001)资助项目. （2020YFB1711001）
