计算机工程与科学2024，Vol.46Issue(8)：1340-1348,9.DOI:10.3969/j.issn.1007-130X.2024.08.002
基于FPGA和行折叠的稀疏矩阵向量乘优化
Optimization of sparse matrix-vector multiplication based on FPGA and row folding
周智 1高建花 1计卫星1
作者信息
- 1. 北京理工大学计算机学院,北京 100081
- 折叠
摘要
Abstract
Sparse matrix-vector multiplication(SpMV)is a key kernel in scientific and engineering computing.Due to the irregular data distribution in sparse matrices and the irregular memory access op-erations in SpMV calculations,the performance of SpMV on multicore CPUs and GPUs still lags signifi-cantly behind the theoretical peak performance of these devices.Existing CPUs and GPUs are limited in their architectures,making them unable to effectively utilize the special structure of sparse matrices to accelerate SpMV calculations.However,Field-Programmable gate arrays(FPGA)can achieve efficient parallel computing through customized circuits,which better handle the computation and storage issues of sparse matrices.An SpMV optimization method based on FPGA is proposed,which utilizes a high-level synthesis streaming processing engine and employs an adaptive multi-row folding SpMV optimiza-tion strategy.This method reduces the ineffective storage and computation of zero elements in the pro-cessing engine through row folding,thereby enhancing the performance of FPGA-based SpMV calcula-tions.Experimental results show that compared to existing FPGA implementations,the proposed row folding-based dataflow engine achieves a maximum speedup of 1.78 times and an average speedup of 1.15 times.关键词
稀疏矩阵向量乘/现场可编程门阵列/高级综合/行折叠Key words
sparse matrix-vector multiplication/field-programmable gate array/high-level synthesis/row folding分类
信息技术与安全科学引用本文复制引用
周智,高建花,计卫星..基于FPGA和行折叠的稀疏矩阵向量乘优化[J].计算机工程与科学,2024,46(8):1340-1348,9.
