集成电路与嵌入式系统2024，Vol.24Issue(10)：31-35,5.DOI:10.20193/j.ices2097-4191.2024.0028
基于BSV的SM3算法硬件实现与优化
Hardware implementation and optimization of SM3 algorithm based on BSV
李可欣 1韩跃平 1聂怀昊1
作者信息
- 1. 中北大学信息与通信工程学院,太原 030051
- 折叠
摘要
Abstract
This article proposes an improved plan for the SM3 algorithm using the agile development language BSV.By analyzing the al-gorithm's operating logic,the algorithm is innovatively split into multiple high-abstraction BSV modules,thereby effectively reducing the design complexity and making it comparable to traditional Verilog design.The code amount is reduced by 60％compared to the previous model.The iterative compression module has a greater impact on the algorithm performance,thus methods such as parallel pipeline and single-round logic optimization are employed for improvement from two aspects,and simulation verification is conducted on the Xilinx ARTIX-7 series FPGA platform with successful serial port debugging.The final results show that only 1 563 LUT resources are con-sumed to achieve a throughput of 3.2 Gbit/s,which represents up to a threefold improvement in throughput per unit logic resource com-pared to existing solutions.The maximum operating frequency reaches 375 MHz,with a higher practical value.关键词
SM3/敏捷开发/BSV/FPGAKey words
SM3/agile development/BSV/FPGA分类
信息技术与安全科学引用本文复制引用
李可欣,韩跃平,聂怀昊..基于BSV的SM3算法硬件实现与优化[J].集成电路与嵌入式系统,2024,24(10):31-35,5.
