集成电路与嵌入式系统2024，Vol.24Issue(11)：86-90,5.DOI:10.20193/j.ices2097-4191.2024.0048
基于权限管理的SoC安全芯片调试系统设计
Design of SoC security chip debug system based on permission management
摘要
Abstract
There are risks of malicious attacks on SoC chips with JTAG/cJTAG interfaces that are not disabled during the mass producti-zation stage,or the JTAG/cJTAG interfaces are simply and permanently disabled by OTP/eFuse,which makes it difficult to locate problems during mass production or limits debugging means when the CPU pointer runs away,making it difficult to locate the problem.This article designs a SoC security chip debug system based on permission management.Compared to traditional debugging methods,this article has made two modifications.For JTAG/cJTAG debugging,permission control bit design,verification password design,and permission comparison design have been added while retaining traditional debugging methods.Regarding the UART debugging method,a UART access register bus design has been added on the basis of retaining traditional debugging methods,and the UART access regis-ter function can be disabled through OTP/eFuse.It not only provides problem analysis methods for SoC chip CPU hanging and pointer running away,but also provides secure and convenient JTAG/cJTAG/UART debugging for SoC chip mass production stage.关键词
权限管理/SoC/调试技术/JTAG/cJTAG/OTP/UARTKey words
permission management/SoC/debug technology/JTAG/cJTAG/OTP/UART分类
信息技术与安全科学引用本文复制引用
刘海亮,吕辉,杨万云..基于权限管理的SoC安全芯片调试系统设计[J].集成电路与嵌入式系统,2024,24(11):86-90,5.基金项目
信息网络安全公安部重点实验室(公安部第三研究所)开放课题基金项目(C22600). （公安部第三研究所）
