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基于国产FPGA的EEPROM读写控制器设计

陈燕 甄国涌 储成群 崔杰

舰船电子工程2024,Vol.44Issue(10):164-169,6.
舰船电子工程2024,Vol.44Issue(10):164-169,6.DOI:10.3969/j.issn.1672-9730.2024.10.034

基于国产FPGA的EEPROM读写控制器设计

Design of EEPROM Read and Write Controller Based on Domestic FPGA

陈燕 1甄国涌 2储成群 2崔杰2

作者信息

  • 1. 陆军装备部驻北京地区军事代表局某军事代表室 太原 030009
  • 2. 中北大学电子测试技术国家重点实验室 太原 030051
  • 折叠

摘要

Abstract

According to the IIC serial communication signal transmission specification,a EEPROM read and write control scheme based on domestic FPGA is designed.Using the domestically produced FPGA chip PGL50G as the core control device,the EEPROM chip is designed with hardware and software modules to control data read and write in bytes.In the circuit design of the hardware module,the signal connection between FPGA and EEPROM is achieved through an external 2.21 K pull-up resistor.In the logic design of software modules,a top-down design approach is adopted to implement the IIC communication protocol used for read and write control according to module division.After the design is completed,signal analysis and verification of the designed read and write controller are carried out using Modelsim SE-64 2020.4 and Pango Design Suite 2022.2-SP3 Debugger tools.The re-sults show that the design method is reasonable,can flexibly configure the EEPROM chip address,and correctly read and write da-ta,which has practical application value.

关键词

FPGA/串行通信/IIC/PGL50G/EEPROM

Key words

FPGA/serial communication/IIC/PGL50G/EEPROM

分类

信息技术与安全科学

引用本文复制引用

陈燕,甄国涌,储成群,崔杰..基于国产FPGA的EEPROM读写控制器设计[J].舰船电子工程,2024,44(10):164-169,6.

基金项目

国家自然科学基金青年科学基金项目(编号:62131018)资助. (编号:62131018)

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