集成电路与嵌入式系统2024，Vol.24Issue(12)：33-37,5.DOI:10.20193/j.ices2097-4191.2024.0046
基于缓冲器的ASIC芯片时序优化设计
Timing optimization design of ASIC chip based on buffer
张祥 1赵启林2
作者信息
- 1. 上海电力大学电子与信息工程学院,上海 201306
- 2. 摩尔精英集成电路发展产业有限公司,上海 201306
- 折叠
摘要
Abstract
With the rapid development of very large-scale integration IC manufacturing process and the continuous improvement of inte-gration,the difficulty of chip timing convergence has become increasingly prominent.The significance of timing,as one of the core inde-xes in the physical design of digital chips,cannot be underestimated.In integrated circuit design,buffers are added to optimize fan-out and reduce interconnect latency,thereby improving timing performance.However,due to the limitations of EDA tools in predicting the position of standard cells,the method of automatically inserting buffers may be unreasonable.This study conducted an in-depth explora-tion of the placement and route design of an ASIC chip using Innovus as a design tool.During the placement stage,an optimized method targeted at buffer insertion was employed.The experimental results indicate that this method significantly improved the design result after placement and route,accelerating the time sequence convergence process.关键词
时序/缓冲器/ASIC芯片/时钟树综合与布局Key words
timing/buffer/ASIC chip/clock tree synthesis and layout分类
信息技术与安全科学引用本文复制引用
张祥,赵启林..基于缓冲器的ASIC芯片时序优化设计[J].集成电路与嵌入式系统,2024,24(12):33-37,5.
