集成电路与嵌入式系统2024，Vol.24Issue(12)：71-78,8.DOI:10.20193/j.ices2097-4191.2024.0034
基于FPGA的LVDS转以太网接口的测试工装
Testing equipment of LVDS to Ethernet interface based on FPGA
文丰 1韩欢 1贾兴中 1杜志美 1王鹤锦1
作者信息
- 1. 中北大学电子测试技术重点实验室仪器科学与动态测试教育部重点实验室,太原 030051
- 折叠
摘要
Abstract
During the dynamic tests on a structural model using wind tunnel experiments,it is necessary to store,record,and analyze the status information of multiple test processes using a data recorder.The data recorder utilizes an LVDS(Low Voltage Differential Signa-ling)interface.To facilitate the issuance of commands and playback tests with an upper computer during the ground phase,an LVDS to Ethernet test fixture was designed.This device employs an FPGA(Field-Programmable Gate Array)as the main control chip,utilizing 8B/10B encoding and decoding to ensure the stability of signal transmission over the LVDS line.Communication with the upper computer is achieved through an Ethernet interface.Data from the recorder is transmitted via LVDS to RAM in the FPGA,and dual RAM buffe-ring is used to enhance transmission efficiency.Subsequently,the data in the RAM is encapsulated into Ethernet UDP/IP frame format.On the basis of the UDP protocol,a command-data"handshake"operation is achieved through alternating dual RAM buffers.CRC(Cy-clic Redundancy Check)verification and data retransmission methods are used to reduce the error rate during transmission.Finally,the data is sent to the upper computer through a physical layer chip.Validation has shown that data transmission using LVDS,FPGA,and Ethernet is feasible,with good stability and reliability,making it suitable for practical engineering applications.关键词
FPGA/LVDS/8B/10B编码/以太网/双RAM缓存/数据重传Key words
FPGA/LVDS/8B/10B code/Ethernet/dual RAM cache/data retransmission分类
信息技术与安全科学引用本文复制引用
文丰,韩欢,贾兴中,杜志美,王鹤锦..基于FPGA的LVDS转以太网接口的测试工装[J].集成电路与嵌入式系统,2024,24(12):71-78,8.
