电讯技术2025，Vol.65Issue(1)：74-80,7.DOI:10.20079/j.issn.1001-893x.231206004
一种带有错误抑制机制的低复杂度Turbo乘积码译码器
A Low-complexity Turbo Product Code Decoder with Error Suppression Mechanism
摘要
Abstract
For the problem of error propagation in the iterative decoding process of Turbo product code(TPC),a very low-complexity error suppression mechanism is designed,which is accurate,simple and efficient in error localization,and can effectively reduce the negative impact of unreliable external information at the beginning of the iteration on the bit error rate(BER)performance.The iterative convergence speed of the proposed decoding algorithm has obvious advantages over the classical Chase algorithm,and in the third iteration,its BER curve can be almost equal to that of the Chase algorithm in four iterations,and the decoding delay can be reduced by 25%under the same performance.At the same time,a soft-input soft-output(SISO)decoder is designed in the field programmable gate array(FPGA),which obtains low decoding latency by parallelizing the test sequence generation module with the syndrome computation module and the Euclidean distance computation module,greatly reduces the arithmetic complexity by using recursive operations,and consumes fewer hardware resources with the same throughput as that of Xilinx's official TPC decoding IP core.关键词
Turbo乘积码/软判决译码/低复杂度/低时延Key words
Turbo product code/soft decision decoding/low complexity/low latency分类
信息技术与安全科学引用本文复制引用
巩克现,闫瑾,刘宏华,王玮..一种带有错误抑制机制的低复杂度Turbo乘积码译码器[J].电讯技术,2025,65(1):74-80,7.基金项目
国家重点研发计划(2019QY0302) （2019QY0302）
国家自然科学基金资助项目(61901417) （61901417）
