计算机工程与科学2025，Vol.47Issue(1)：10-17,8.DOI:10.3969/j.issn.1007-130X.2025.01.002
DSP处理器二级缓存的结构优化研究
Structure optimization of second-level Cache in DSP processor
安昕辰1
作者信息
- 1. 南京信息工程大学电子与信息工程学院,江苏 南京 210044||中国电子科技集团公司第五十八研究所,江苏 无锡 214072
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摘要
Abstract
In recent years,emerging applications in fields such as autonomous driving,medical in-struments,and smart homes have placed higher demands on the real-time performance and data throughput capabilities of DSP processors.The use of multi-level cache structures in DSPs introduces la-tency uncertainties due to processes such as cache misses and coherency maintenance.Aiming at allevi-ating the performance degradation caused by long delay access,the method of combining miss status holding registers and victim buffer into one structure is proposed.This structure allocates its item func-tion flexibly at runtime to improve buffer utilization.Aiming at the low synchronization efficiency of co-herency maintenance information between L1 Cache and L2 Cache,this paper proposes to use the conti-nuity between invalid addresses to synchronize invalid information to the snoop filter without blocking.The test results show that the performance of the producer-consumer scenario program with many dirty data updates is improved by 19.91%,and the synchronization time of 32 lines of invalid information de-creased from 61 cycles to 16 cycles.关键词
DSP/二级缓存/流水线/一致性Key words
digital signal processer(DSP)/L2 Cache/pipeline/coherency分类
信息技术与安全科学引用本文复制引用
安昕辰..DSP处理器二级缓存的结构优化研究[J].计算机工程与科学,2025,47(1):10-17,8.
