计算机工程与科学2025，Vol.47Issue(1)：27-34,8.DOI:10.3969/j.issn.1007-130X.2025.01.004
面向Duobinary信号的时钟恢复电路研究与设计
Research and design of clock recovery circuit for Duobinary signal
摘要
Abstract
High-speed serial interfaces serve as the interconnect core between chips in high performance computer systems.Addressing the high bandwidth requirements for high-speed serial communication,the design and simulation of a 56 Gbps Duobinary signal clock and data recovery(CDR)circuit were completed based on Verilog-AMS on the Candence platform.Multi-level transmission can reduce the de-mand for bandwidth.The CDR circuit was designed using a phase interpolator(PI),with the phase de-tection results from a Bang-Bang phase detector serving as the basis for phase discrimination.Digital signal processing(DSP)algorithms,including a voting algorithm,filtering algorithm,and phase con-trol code conversion algorithm,were employed to process the phase detection results.The digital algo-rithms reduced the complexity of the circuit design,facilitated the adjustment of loop gain,improved system stability,and decreased loop delay.Simulation results demonstrate that the CDR circuit can track phase differences and frequency offsets of 100 PPM.By adding a 0.25 UI sinusoidal jitter to the in-put data,with a loop bandwidth of 23 MHz,the system can track the sinusoidal jitter when the jitter frequency does not exceed the loop bandwidth.The jitter tolerance meets the specifications of the CEI-56G protocol.关键词
时钟数据恢复/Duobinary信号/Bang-Bang鉴相器/数字信号处理算法/正弦抖动Key words
clock and data recovery(CDR)/Duobinary signal/Bang-Bang phase detector/digital sig-nal processing(DSP)algorithm/sinusoidal jitter分类
信息技术与安全科学引用本文复制引用
袁梁勇,齐星云,吕方旭,罗章,黄恒,张庚,王文晨,李萌,赖明澈..面向Duobinary信号的时钟恢复电路研究与设计[J].计算机工程与科学,2025,47(1):27-34,8.基金项目
国家重点研发计划(2021YFB2206600) （2021YFB2206600）
