舰船电子工程2025，Vol.45Issue(1)：127-131,5.DOI:10.3969/j.issn.1672-9730.2025.01.025
二元扩域下的低延迟SM2加密FPGA实现
Low-latency FPGA Implementation of SM2 Encryption in Binary Extension Fields
摘要
Abstract
To address the demand for low-latency encryption in modern security domains,this paper investigates the overall computation process of SM2 encryption based on the Montgomery elliptic curve point multiplication algorithm.The SM2 encryption algorithm is firsty decomposed into multiple independent steps and mapped to specific FPGA modules.Subsequently,the computa-tion timing of each module is arranged in a parallel manner,resulting in a low-latency FPGA implementation method.The proposed method is used to perform SM2 encryption over GF(2256)requires 4 102 clock cycles,while over GF(2512)it requires 8 198 clock cy-cles,representing a 20%reduction in clock cycles compared to traditional serial computation methods.Finally,the proposed meth-od is implemented on the Xilinx Virtex-7 platform,where performing SM2 encryption over GF(2256)takes 43.31 microseconds,and over GF(2512)takes 109.47 microseconds.关键词
SM2加密/FPGA/椭圆曲线点乘/Montgomery算法Key words
SM2 encryption/FPGA/ECPM/Montgomery algorithm分类
信息技术与安全科学引用本文复制引用
臧帅辰,储成群,甄国涌..二元扩域下的低延迟SM2加密FPGA实现[J].舰船电子工程,2025,45(1):127-131,5.基金项目
国家自然科学基金项目(编号:62131018) （编号:62131018）
山西省科技重大专项计划"揭榜挂帅"项目(企业重大技术攻关类)"工控系统可信安全环境构建关键技术研究"(编号:202101010101017)资助. （企业重大技术攻关类）
