集成电路与嵌入式系统2025，Vol.25Issue(3)：33-40,8.DOI:10.20193/j.ices2097-4191.2024.0050
MIPS处理器核及其定制化AXI总线设计
MIPS processor core and customized AXI bus design
周艳娇 1贾艳双 1杜军1
作者信息
- 1. 哈尔滨师范大学计算机科学与信息工程学院,哈尔滨 150025
- 折叠
摘要
Abstract
To address the issues of high resource utilization and poor customizability associated with using pre-built AXI interface IP cores,a phased,self-designed approach is proposed to add AXI bus support to a designed MIPS processor core.The design is implemen-ted using Verilog HDL for writing RTL code.The overall logic functionality of the processor was verified in the Vivado simulation envi-ronment,and the bitstream file was downloaded to the FPGA development board for prototype verification to obtain utilization and timing.Finally,the processor is synthesized using the Design Compiler(DC)tool,and the overall area and power consumption of the processor are evaluated.The verification results indicate that the self-designed AXI bus consumes fewer resources and occupies less area compared to directly using an AXI interface IP core.Furthermore,this approach ensures that the AXI bus is added without changing the processor core architecture,significantly reducing the difficulty of replacing the original interface in the processor core with the AXI bus interface.It not only reduces integration complexity but also ensures a high degree of customization to meet specific system requirements and performance demands.关键词
AXI IP核/MIPS/处理器核/六级流水线Key words
AXI IP core/MIPS/processor core/six-stage pipeline分类
计算机与自动化引用本文复制引用
周艳娇,贾艳双,杜军..MIPS处理器核及其定制化AXI总线设计[J].集成电路与嵌入式系统,2025,25(3):33-40,8.
