机电工程技术2025，Vol.54Issue(4)：56-61,117,7.DOI:10.3969/j.issn.1009-9492.2025.04.009
考虑TSV的三维集成电路布局方法研究
Study on Three-dimensional Integrated Circuit Placement Method Considering TSV
摘要
Abstract
With the continuous development of electronic devices,two-dimensional(2D)circuit placement has been unable to meet the increasing functional and performance requirements,and at the same time,the interconnection delay between circuit components(units)has become the bottleneck restricting the development of integrated circuits(IC).To overcome this challenge,three-dimensional(3D)integration technology has emerged to enable higher integration and shorter signal transmission paths by stacking circuits in a vertical direction.However,three-dimensional integrated circuit(3D IC)design also introduces the problem of layer-to-layer communication components(through-silicon,TSV).TSV is expensive,and will occupy a lot of chip area,in addition,the unreasonable placement of TSV will affect the wiring resources,increase the chip interconnect length.Therefore,it is important to consider the size and position of the TSV in 3D IC placement.In order to solve the above two problems,a three-dimensional placement method of integrated circuits considering TSV is proposed.The method first divides the circuit into two partitions,then global placement of the TSV,then global placement of the top and bottom layers according to the position of the TSV,and finally legalize the cell and TSV,detailed placement and localiterative tuning.The experimental results based on the ICCAD 2023 benchmark test circuit show that the proposed algorithm reduces the TSV number by 96%on average compared with the current optimal 3D IC placement algorithm.关键词
三维布局/划分/TSV/最小化总线长Key words
three-dimensional placement/partition/TSV/minimize wire length分类
信息技术与安全科学引用本文复制引用
李荣,魏丽军..考虑TSV的三维集成电路布局方法研究[J].机电工程技术,2025,54(4):56-61,117,7.基金项目
国家自然科学基金项目(7227010125) （7227010125）
