空天预警研究学报2025，Vol.39Issue(1)：61-66,6.DOI:10.3969/j.issn.2097-180X.2025.01.012
基于斩波稳定的SAR Sigma-Delta调制器的设计
Design of a chopper-stabilized SAR Sigma-Delta modulator
摘要
Abstract
In order to achieve high-precision and low-power consumption of analog-to-digital converter(ADC),chopper stabilization technology is used to eliminate operational amplifier offset and circuit noise.Multi-bit quantization architecture is employed to optimize circuit performance.By combining the characteristics of successive approximation register(SAR)ADC's low-power consumption and fast speed with the advantages of Sigma-Delta ADC's high precision,a SAR Sigma-Delta hybrid-architecture modulator is proposed.This modula-tor circuit is implemented by using the smic 180 nm CMOS process.Under a 1.8 V input condition with a signal bandwidth of 1 kHz and a sampling rate of 0.512 MHz,such results are obtained as the maximum signal to noise ratio(SNR)of the output signal of 115.05 dB,a spurious-free dynamic range(SFDR)of 120.09 dB,an effective number of bits(ENOB)of 18.8 bits,an area of only 0.81 mm2,and power consumption as low as 1.09 mW.关键词
Sigma-Delta调制器/斩波稳定技术/多位量化/低功耗/高精度Key words
Sigma-Delta modulator/chopper stabilization technology/low power consumption/high preci-sion分类
电子信息工程引用本文复制引用
谢烜程,蔡孟冶,姜岩峰..基于斩波稳定的SAR Sigma-Delta调制器的设计[J].空天预警研究学报,2025,39(1):61-66,6.基金项目
国家重点研究计划项目(2024YFB4505405) （2024YFB4505405）
