空天预警研究学报2025，Vol.39Issue(1)：67-73,7.DOI:10.3969/j.issn.2097-180X.2025.01.013
基于FPGA与PCIe的回波模拟器采集组件设计
Design of acquisition component for echo simulator based on FPGA and PCIe
李森 1王建明 1唐吉林1
作者信息
- 1. 中国兵器装备集团自动化研究所有限公司,四川 绵阳 621000
- 折叠
摘要
Abstract
Aimed at the problem of low bus utilization of the Controller Area Network(CAN)communica-tion interface of the radar echo simulator acquisition component,a design method of"pipelining instruction,data configuration+automatic reading"for the echo simulator acquisition component is proposed.Eight analog-to-dig-ital converter(ADC)chips are used to perform parallel real-time sampling of data from eight channels.A fast me-dian average filtering algorithm is adopted to meet the low-delay requirement of ADC data filtering.For the User Datagram Protocol(UDP)communication function of the echo simulator acquisition component,an Ethernet UDP protocol stack supporting 10/100/1000 Mbps three-speed adaptive is designed.Finally,this method is designed and implemented on the Field Programmable Gate Array(FPGA).The actual test results show that the bus utiliza-tion of the CAN communication interface is increased from the original 42.29%to 79.80%,that the filtering delay of ADC data is only one clock cycle,and the phase is aligned,and that the communication function of the UDP protocol stack correctly meets the design requirements.关键词
现场可编程门阵列/外设组件互连扩展总线/控制器局域网通信/快速中值滤波/UDP协议栈Key words
FPGA/peripheral component interconnect express(PCIe)/CAN communication/fast median fil-tering/UDP protocol stack分类
电子信息工程引用本文复制引用
李森,王建明,唐吉林..基于FPGA与PCIe的回波模拟器采集组件设计[J].空天预警研究学报,2025,39(1):67-73,7.
