液晶与显示2025，Vol.40Issue(3)：448-456,9.DOI:10.37188/CJLCD.2024-0198
基于CNN的异构FPGA硬件加速器设计
Design of heterogeneous FPGA hardware accelerator based on CNN
摘要
Abstract
Due to limitations in hardware platform computing power and storage resources,achieving energy-efficient and efficient convolutional neural networks(CNNs)by using embedded systems remains a primary challenge for hardware designers.In this context,a complete design of a heterogeneous embedded system implemented by using a system-on-chip(SoC)with a field-programmable gate array(FPGA)is proposed.This design adopts a cascaded input multiplexing structure,enabling two independent multiply-accumulate operations in a single DSP,reducing external memory access,enhancing system efficiency,and lowering power consumption.Compared to other designs,the power efficiency is improved by over 38.7%.The design framework is successfully deployed in a large-scale CNN network on low-cost devices,significantly improving power efficiency of the network model.The power efficiency achieved on the ZYNQ XC7Z045 device can even reach 102 Gops/W.Furthermore,when inferring the VGG-16's CONV layers by using this framework,a frame rate of up to 10.9 fps is achieved,which demonstrates the framework's effective acceleration of CNN inference in power-constrained environments.关键词
硬件加速/卷积神经网络/FPGA/异构SoCKey words
hardware acceleration/convolutional neural network/FPGA/heterogeneous SoC分类
计算机与自动化引用本文复制引用
籍浩林,徐伟,朴永杰,吴晓斌,高倓..基于CNN的异构FPGA硬件加速器设计[J].液晶与显示,2025,40(3):448-456,9.基金项目
钱学森空间技术实验室创新工作站开发基金(No.GZZKFJJ2020003) Supported by Qian Xuesen Laboratory of Space Technology Innovation Workstation Development Foundation(No.GZZKFJJ2020003) （No.GZZKFJJ2020003）
