集成电路与嵌入式系统2025，Vol.25Issue(4)：1-9,9.DOI:10.20193/j.ices2097-4191.2024.0086
基于FPGA的高效蒙哥马利模乘器设计
Design of an efficient Montgomery modular multiplier based on FPGA
摘要
Abstract
To achieve high parallel computing,fully homomorphic encryption hardware acceleration systems require the instantiation of a large number of cryptographic primitive operation units.As the most crucial primitive operation in fully homomorphic encryption,the circuit implementation area of modular multiplication significant impacts the overall area of the acceleration system.Addressing issues such as excessive resource usage,limited parameter,and dependency on macro core IPs in existing modular multiplier designs,this pa-per presents an efficient Montgomery modular multiplier based on FPGA.At the algorithmic level,the multiplier reduces the computa-tional load through techniques such as NTT-Friendly modulus characteristics,compression,and encoding.At the circuit level,it mini-mizes resource through methods like time-division and data integration.Furthermore,the multiplier supports parameter configuration to implement Montgomery modular multiplication for different widths.Experimental results demonstrate that,for a 32-bit width,the de-signed Montgomery modular multiplier operates at a clock frequency of 223 MHz with a latency of 26.9 ns,utilizing 1 313 LUTs and 213 FFs.Compared to the baseline,the resource consumption is reduced by 32％on average,while the latency is improved by 16％on average,making the design more flexible and highly applicable.关键词
蒙哥马利模乘/FPGA/编码/压缩/同态加密Key words
Montgomery modular multiplication/FPGA/encode/compression/homomorphic encryption分类
电子信息工程引用本文复制引用
颜震,黄亦成,马仕成,王雪岩..基于FPGA的高效蒙哥马利模乘器设计[J].集成电路与嵌入式系统,2025,25(4):1-9,9.基金项目
中央高校基本科研业务费专项资金资助. （）
