电子科技2025，Vol.38Issue(5)：15-21,7.DOI:10.16180/j.cnki.issn1007-7820.2025.05.003
R-DSP中BSU运算部件的UVM验证
UVM Verification of BSU Arithmetic Unit in R-DSP
摘要
Abstract
In view of the problem that the BSU(Branch Shift Unit)arithmetic unit in the R-DSP(Radar Digit-al Signal Processor)chip has a large design scale and complexity,and the traditional Verilog verification platform is difficult to meet its verification requirements,this study adopts the UVM(Universal Verification Methodology)to con-duct functional verification of the BSU arithmetic unit.A UVM verification platform implemented based on the System-Verilog language is constructed.Directed testing and constrained random testing are utilized for verification,and the coverage-driven approach is adopted to guide the generation of test cases,so as to fully cover all functions and code paths of the BSU arithmetic unit.After multiple rounds of verification with test stimuli,the code coverage approaches 100%,and the functional verification of the BSU arithmetic unit is completed.The proposed method provides a refer-ence for the verification work of arithmetic units such as the ALU(Arithmetic Logic Unit),AGU(Address Generation Unit),and MU(Multiplication Unit)in the R-DSP chip.关键词
BSU运算部件/功能验证/UVM方法/SystemVerilog语言/定向测试/约束随机测试/覆盖率驱动/代码覆盖率Key words
BSU computing unit/functional verification/UVM method/SystemVerilog language/directed test/constrainted random test/coverage driven/code coverage分类
电子信息工程引用本文复制引用
郭双喜,谭勋琼,白创..R-DSP中BSU运算部件的UVM验证[J].电子科技,2025,38(5):15-21,7.基金项目
湖南省教育厅优秀青年科研项目(22B0287) Research Foundation of Education Bureau of Hunan(22B0287) （22B0287）
