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支持FPGA动态重构的RISC-V扩展指令集设计与实现

周炫锦 蔡刚 黄志洪

计算机工程2025,Vol.51Issue(5):229-238,10.
计算机工程2025,Vol.51Issue(5):229-238,10.DOI:10.19678/j.issn.1000-3428.0069267

支持FPGA动态重构的RISC-V扩展指令集设计与实现

Design and Implementation of RISC-V Extended Instruction Set Supporting FPGA Dynamic Reconfiguration

周炫锦 1蔡刚 1黄志洪2

作者信息

  • 1. 中国科学院空天信息创新研究院,北京 100094||中国科学院大学电子电气与通信工程学院,北京 100049
  • 2. 中国科学院空天信息创新研究院,北京 100094
  • 折叠

摘要

Abstract

Currently,dynamic refactoring is implemented by configuring it through on-chip interfaces,usually using the dynamic refactoring control Intellectual Property(IP)core provided by the official Field Programmable Gate Array(FPGA),and connected to the processor through the system bus.This method consumes a significant amount of static logic resources and limits the frequency of the on-chip interfaces.To address these issues,this study proposes the design concept of abstracting an FPGA as large-scale memory.A Dynamic Partial ReConfiguration(DPRC)dynamic reconstruction control instruction set and supporting Application Programming Interface(API)are constructed to optimize the usage of logic resources and eliminate buffer latency.The instruction set is implemented based on the original RV32IMC,using microinstruction sequences to control the on-chip interface part.By tightly coupling with the data path,logic resource usage is reduced,and a parameterized multicycle scheme is used to optimize the timing and ensure generality.Experimental results show that,compared with traditional methods,the dynamic reconstruction function in this system reduces the logical resource usage by 84%and increases the frequency by 312%.Compared with the original processor,the addition of an extended instruction set increases the resource usage of the processor alone by 5%.In the worst case,the impact of the extended part on the clock cycle is less than 0.2 ns,which shows that this dynamic reconstruction control scheme has the characteristics of low cost and high clock frequency.

关键词

RISC-V指令集/扩展指令集/动态重构/FPGA技术/大规模存储器

Key words

RISC-V instruction set/extended instruction set/dynamic reconfiguration/FPGA technology/large scale memory

分类

信息技术与安全科学

引用本文复制引用

周炫锦,蔡刚,黄志洪..支持FPGA动态重构的RISC-V扩展指令集设计与实现[J].计算机工程,2025,51(5):229-238,10.

基金项目

国家自然科学基金(61704173). (61704173)

计算机工程

OA北大核心

1000-3428

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