计算机工程与科学2025，Vol.47Issue(4)：612-620,9.DOI:10.3969/j.issn.1007-130X.2025.04.005
基于FPGA的高速AES实现与列混合改进
Implementation of high-speed AES based on FPGA and improvement of MixColumn
摘要
Abstract
A high-speed communication implementation scheme for AES based on FPGA is pro-posed.By splitting the encryption process into a 30-level parallel pipeline structure,communication speed and encryption efficiency can be improved.At the same time,based on the special GF(28)finite field operation rules of the MixColumn parts in AES and the structural characteristics of FPGA parallel operation,an intermediate cross-MixColumn structure is designed.This structure can effectively reduce the computational delay and usage area of MixColumn and inverse MixColumn parts,and improve the encryption efficiency.From the perspective of logical algebra,the differences in computational resource usage between traditional MixColumn structures,newer MixColumn structures,and inter-mediate cross computing structures are analyzed.Finally,the verification results on Xilinx's XC5VSX240T chip show that the proposed scheme achieves a throughput of 60.928 Gbps and an encryption efficiency of 14.875 Mbps/LUT.关键词
FPGA/AES加密算法/列混合/流水线Key words
FPGA/AES encryption algorithm/MixColumn/pipeline分类
计算机与自动化引用本文复制引用
申锦尚,张庆顺,宋铁锐..基于FPGA的高速AES实现与列混合改进[J].计算机工程与科学,2025,47(4):612-620,9.基金项目
河北大学科研创新团队支撑项目(IT2023B05) （IT2023B05）
