计算机应用与软件2025，Vol.42Issue(4)：107-113,165,8.DOI:10.3969/j.issn.1000-386x.2025.04.017
基于可变编码块流水的可重构HEVC帧内环路设计
DESIGN OF RECONFIGURABLE HEVC INTRA-LOOP BASED ON VARIABLE CODING BLOCK PIPELINE
摘要
Abstract
During the hardware implementation of the high efficiency video coding standard(HEVC),its high computational complexity and high data dependence not only hinder the performance of real-time video encoding,but also bring higher resource consumption.In this paper,we analyzed the data/timing dependency relationship between the various algorithms of the intra-frame loop when processing pixel blocks,and the HEVC intra-loop reconfigurable array structure based on the variable coding block pipeline is completed.By using the adjacent interconnection interface between the modules,the handshake communication realized the pipeline processing between the entire intra-frame loop coding blocks,and improved the calculation efficiency of the intra-frame loop.The experimental results show that the proposed method meets the requirements of computing speed and hardware resources.Compared with the serial-based intra-loop encoding processing circuit,the execution time is reduced by 87％,and the clock frequency reaches 125 MHz.关键词
可变编码块流水/可重构阵列处理器/高效视频编码/帧内环路/邻接互连Key words
Variable coding block pipeline/Reconfigurable array processor/High efficiency video coding/Intra-frame loop/Adjacent interconnection分类
信息技术与安全科学引用本文复制引用
夏馨缘,山蕊,崔馨月,杨坤,廖望..基于可变编码块流水的可重构HEVC帧内环路设计[J].计算机应用与软件,2025,42(4):107-113,165,8.基金项目
国家自然科学基金项目(61802304,61834005,61772417,61602377,61634004). （61802304,61834005,61772417,61602377,61634004）
