集成电路与嵌入式系统2025，Vol.25Issue(5)：24-34,11.DOI:10.20193/j.ices2097-4191.2025.0004
面向高性能DSP的一级可配置指令缓存设计与验证
Design and verification of level-1 configurable instruction cache for high-performance DSP
摘要
Abstract
To address the issue of caches being unable to predict nonlocal program execution and prepare for critical tasks,this paper pro-poses a high-security,level-1 configurable instruction cache design.The design achieves flexible Cache/SRAM configurability through internal control registers.It ensures data access security for users at various levels through two granularity storage protection mecha-nisms:page-level and cache line-level.Rapid interaction with external storage data is achieved through direct memory access(DMA)to SRAM.A Universal Verification Methodology(UVM)verification platform is established to conduct module-level verification of the configurable instruction cache and collect coverage data.Different library functions are invoked to perform system-level verification and compare the hit rates of the cache under different L1P size configurations.A 40 nm low-threshold library is utilized to conduct post-sim-ulation verification of latency and power consumption.The results demonstrate that the designed cache can safely and swiftly switch be-tween five L1P configurations of 32 KB,16 KB,8 KB,4 KB,and 0 KB during program execution,with a maximum path delay of 1.47 ns and a total power consumption of 309.577 mW,meeting the stable operation requirements of a 600 MHz high-performance DSP.关键词
一级指令缓存/UVM验证学/存储保护/DSP/CacheKey words
level-1 instruction cache/UVM verification/memory protection/DSP/Cache分类
计算机与自动化引用本文复制引用
唐俊龙,高睿禧..面向高性能DSP的一级可配置指令缓存设计与验证[J].集成电路与嵌入式系统,2025,25(5):24-34,11.基金项目
湖南省制造业关键产品"揭榜挂帅"项目高性能高可靠国产DSP芯片项目(2022GXGG012). （2022GXGG012）
