陕西科技大学学报2025，Vol.43Issue(3)：174-180,7.
轮内流水线型SM4算法的FPGA优化
FPGA optimization of the in-round pipelined SM4 algorithm
摘要
Abstract
Aiming at the problems of complex structure and slow operation speed during the implementation of SM4 algorithm in field programmable gate array(FPGA),the FPGA im-plementation of SM4 algorithm is further optimized based on the pipelining idea.Multiple FPGA implementation strategies of SM4 algorithm are analyzed,and the critical path of each implementation strategy is found.The FPGA implementation strategy of the SM4 algorithm S-box is improved by splitting the S-box operation into lookup table(LUT)level storage op-eration and implementing it based on the LUT primitive,which reduces the complexity of the S-box operation.An improved in-round pipelined SM4 algorithm is proposed to shorten the critical path of the algorithm to a single-level LUT operation.The improved algorithm is syn-thesized and implemented based on the ZYNQ-7020 development board,and the realized scheme has a running clock frequency of 518 MHz and a throughput of 66.30 Gb/s,which is better than the existing scheme.关键词
SM4算法/FPGA/流水线结构Key words
SM4 algorithm/FPGA/pipeline structure分类
信息技术与安全科学引用本文复制引用
郭宇,贾小云,蒋建伟,杨振英,段克盼..轮内流水线型SM4算法的FPGA优化[J].陕西科技大学学报,2025,43(3):174-180,7.基金项目
国家自然科学基金项目(61971272) （61971272）
