福建电脑2025，Vol.41Issue(6)：45-48,4.DOI:10.16707/j.cnki.fjpc.2025.06.009
时序逻辑乘法器设计
Design of Sequential Logic Multiplier
罗海涛1
作者信息
- 1. 广东外语外贸大学信息科学与技术学院 广州 510420
- 折叠
摘要
Abstract
As a fundamental operation of ALU,multiplication covers the principles and processes of computer data processing and digital circuit design.To guide students in analyzing the process of binary number multiplication,this article introduces the design of a two bit multiplier for basic logic devices.This design case can help stimulate students'interest in learning in teaching.关键词
乘法运算/时序逻辑乘法器/电子设计自动化Key words
Multiplication Operation/Sequential Logic Multiplier/Electronic Design Automation分类
信息技术与安全科学引用本文复制引用
罗海涛..时序逻辑乘法器设计[J].福建电脑,2025,41(6):45-48,4.
