集成电路与嵌入式系统2025，Vol.25Issue(6)：29-38,10.DOI:10.20193/j.ices2097-4191.2025.0018
基于DSP IP核的双模态可配置软PUF
Dual-modal configurable software PUF based on DSP IP core
摘要
Abstract
With the rapid advancement of information technology and artificial intelligence,the increasingly complex functions of IoT ter-minal devices have resulted in significant security threats due to their limited hardware resources.To address this,this paper proposes a dual-mode configurable software PUF(Physical Unclonable Function)design based on the DSP IP core.This approach leverages the timing violation behavior characteristics of sampling registers and the combinational logic delay features within the DSP IP core of FPGA.First,the internal structure of DSP IP cores in Xilinx Artix-7 FPGA is analyzed,determining the clock cycle range for normal data transmission based on their combinational logic delay information and timing constraints.Next,two distinct operational modes are configured based on the required challenge bit length,with overclocked clocks applied to induce abnormal computational results through timing violation in the sampling registers.Finally,a hash algorithm and parity check are used to compress the abnormal data of varying bit lengths into a 1-bit PUF response.This design eliminates the need for additional bias extraction circuits and allows for flexible config-uration of two different challenge bit lengths for the software PUF implementation without modifying the hardware structure.The ex-perimental results demonstrate that both operational modes achieve a reliability of over 98％,with excellent uniqueness and resistance to machine learning attacks,thereby validating the proposed scheme's feasibility and advantages in terms of both security and practicality.关键词
物理不可克隆函数/时序违例/DSP IP核/硬件安全Key words
physical unclonable function/timing violation/DSP IP core/hardware security分类
电子信息工程引用本文复制引用
郑紫阳,汪鹏君,李刚,陈博,杨欣荣,李翔宇..基于DSP IP核的双模态可配置软PUF[J].集成电路与嵌入式系统,2025,25(6):29-38,10.基金项目
国家自然科学基金项目(62174121,62234008) （62174121,62234008）
