集成电路与嵌入式系统2025，Vol.25Issue(6)：39-47,9.DOI:10.20193/j.ices2097-4191.2025.0020
万兆以太网高带宽低延迟接口的FPGA轻量化设计
FPGA-based lightweight design of 10 GbE high-bandwidth low-latency interface
摘要
Abstract
The real-time simulation of new power system puts forward higher requirements for CPU-FPGA heterogeneous computing and multi-FPGA distributed computing,in which communication efficiency may become one of the bottlenecks.Given the current limitations of Gigabit Ethernet in bandwidth and real-time performance,this paper proposes an FPGA-based lightweight design of 10 GbE high-bandwidth low-latency interface.PHY is built based on the GT to achieve low latency and high reliability.In the UDP stack,alternating caching and queuing with priority are adopted to improve data throughput and balance instantaneous load.The on-board test results show that the design achieves low hardware resource consumption,a maximum transmission bandwidth of 9.70 Gb/s,an average trans-mission delay of 0.45 μs and stable interactions between protocol layers without interference,which provides efficient communication support for the simulation of power system and other applications.关键词
FPGA/万兆以太网/UDP/交替缓存/硬件接口Key words
FPGA/10GbE/UDP/alternating caching/hardware interface分类
计算机与自动化引用本文复制引用
宋驰峰,杨航宇,刘济源,汤勇明,袁晓冬,李鹤..万兆以太网高带宽低延迟接口的FPGA轻量化设计[J].集成电路与嵌入式系统,2025,25(6):39-47,9.基金项目
国家电网有限公司总部科技项目资助(5400-202318547A-3-2-ZN) （5400-202318547A-3-2-ZN）
