电子科技2025，Vol.38Issue(6)：9-15,7.DOI:10.16180/j.cnki.issn1007-7820.2025.06.002
基于FPGA-TDC的随机同步误差校正电路
Random Synchronization Error Correction Circuit Based on FPGA-TDC
摘要
Abstract
In view of the problem that the random synchronization error in multiple-channel radar receivers leads to the difficulty in aligning the echo signal data between the acquisition channels,this study designs an all-dig-ital random synchronization error correction circuit.High-precision time measurement technology based on the FPGA-TDC(Field Programmable Gate Array-Time-to-Digital Converter)is used to measure the phase difference between the arrival moment of the external trigger and the rising edge of the system clock.The phase compensation step size is determined from the phase difference information after encoding and calibration.The dynamic phase shifting mode of the MMCM(Mixed-Mode Clock Manager)in the FPGA is used to finely adjust the clock phase,and complete the high-precision synchronization between the system clock and the pulse echo signal.Test results show that the accura-cy of the proposed circuit is better than 70 ps rms(root mean square),and the correction time is less than 12 μs,indicating that the proposed method is able to deal with the random synchronization error problem quickly.关键词
随机同步误差/多通道采集系统/误差校正/FPGA/时间数字转换/相位补偿/动态移相/MMCMKey words
random synchronization error/multiple-channels data acquisition system/error correction/FPGA/time to digital convert/phase compensation/dynamic phase shift/MMCM分类
电子信息工程引用本文复制引用
姚晓晨,徐杨,郑其斌,卜朝晖,唐高明,崔海坡..基于FPGA-TDC的随机同步误差校正电路[J].电子科技,2025,38(6):9-15,7.基金项目
国家自然科学基金(12105177) （12105177）
上海航天科技创新基金(SAST2022-094)National Natural Science Foundation of China(12105177) （SAST2022-094）
Shanghai Aerospace Science and Technology Innovation Fund(SAST2022-094) （SAST2022-094）
