计算机工程与科学2025，Vol.47Issue(6)：968-975,8.DOI:10.3969/j.issn.1007-130X.2025.06.003
基于多操作数的RISC-Ⅴ指令集设计与功能优化方法
Designing and optimizing RISC-Ⅴ instruction set functionality based on multi-operand acceleration
张钰儿 1席宇浩 1刘鹏1
作者信息
- 1. 浙江大学信息与电子工程学院,浙江 杭州 310027
- 折叠
摘要
Abstract
The RISC-Ⅴ architecture,with its open and modular instruction set architecture(ISA)de-sign,facilitates the integration of customized instructions tailored to specific applications and their soft-ware ecosystems,enabling efficient processing of complex algorithms and repetitive operations.Howev-er,designing acceleration instructions for RISC-Ⅴ processors presents significant challenges,primarily due to limitations in operand quantity.Traditional acceleration methods typically adopt a 2-input-1-output model,which restricts the flexibility and efficiency of complex operations.To address these limi-tations,this method proposes a multi-operand acceleration mechanism that breaks the conventional 2-in-put-1-output constraint by providing a flexible interface for multiple inputs and outputs.The mechanism is validated through benchmark tests on an FPGA platform,including SHA-256,SHA-1,and FIR/IIR filter algorithms,conducted on Western Digital's open-source RISC-Ⅴ VeeR EH1 core.Experimental results demonstrate a performance improvement of up to 14％while maintaining hardware overhead at or below 3％.Compared to traditional 2-input-1-output acceleration methods,the proposed enhanced instruction set design significantly enhances the processing efficiency of RISC-Ⅴ cores,demonstrating its superior capability in embedded computing and domain-specific acceleration applications.关键词
RISC-Ⅴ/自定义指令/软硬件协同设计Key words
reduced instruction set computer-Ⅴ(RISC-Ⅴ)/custom instructions/hardware-software co-design分类
计算机与自动化引用本文复制引用
张钰儿,席宇浩,刘鹏..基于多操作数的RISC-Ⅴ指令集设计与功能优化方法[J].计算机工程与科学,2025,47(6):968-975,8.
